TBwcet®

What is TBwcet?

Across many industries, real-time closed-loop control applications depend on predictable execution such that specific activities must repeatedly complete within narrow timing constraints. As a result, developers are required to demonstrate that these activities can always finish within the allowed timeframe, even under worst-case conditions. This expectation is formally mandated by numerous safety-related standards, including DO-178C, IEC 61508, ISO 26262, and others.

Real-time, closed-loop control systems across the sectors rely on the deterministic completion of defined tasks within tight time windows to gather data, process it, and update the system. That places the onus on developers to ensure that the completion of these tasks is achievable even in the worst case.

Multicore processors make matters even more challenging because of interference channels resulting from shared resources.

How do timing analysis considerations differ across hardware architectures?

The presence of shared resources in multicore processors (MCPs) introduces interference effects that make purely analytical timing estimation impractical, necessitating measurement on the actual target to confirm sufficient provisioning and effective mitigation.

On single-core devices, contention for internal resources still limits the accuracy of theoretical analysis, meaning first-principles approaches must be applied cautiously or supplemented with empirical measurement techniques

How does TBwcet support timing analysis?

TBwcet adopts a proven test harness “wrapper” principle which provides the means to repeatedly execution a subset of the application and analyse the resulting execution times.

It affords the flexibility to perform execution time analysis from complete threads or processes right down to class/function/procedure level. This approach provides the ability to “drill in” to problem areas.

The choice of stressor mechanism is left to the user. Open-source solutions such as Stress ng provides specific stressors for Hardware Shared Resources (HSRs) such as

built-in registers,
cache,
ram,
virtual memory

The flexibility of the test harness presents the opportunity for these stressors to be adapted to suit specific circumstances, or for new ones to be developed from first principles.

In combination with the TBexec component of the LDRA tool suite, TBwcet addresses the resource usage evaluation demands of automotive standard ISO 26262. WCET analysis is also specified for aviation applications in CAST 32A and A(M)C 20-193, and these also demand data and control coupling analysis to highlight possible interference scenarios. Appropriate coupling coverage analysis is also supported by the LDRA tool suite.

How are TBwcet results presented?

TBwcet results are available in several formats, with the graphical format being particularly intuitive to use. The results below show a set of results from a test run with no apparent interference effects.

In practice, as the effects of interference become apparent the mean execution time becomes longer, and the spread of results becomes wider:

How is TBwcet complementary to TBexec?

TBexec and TBwcet combine to provide a complete timing assurance solution, and address the objectives defined by A(M)C 20-193 for multicore processors.

TBexec records and visualizes execution timing at both function and application level, exposing interactions, parallel activity, and ordering effects as they occur in real operation. TBwcet augments this capability by determining Worst-Case Execution Time (WCET) for selected portions of an application under controlled conditions, including scenarios that introduce interference.

Together, these tools allow the effects of shared resource contention on individual software elements to be measured and assessed. They provide a combination of high-level behavioural understanding and rigorous worst-case substantiation, helping to meet verification goals and, where appropriate, addressing multicore interference requirements.

MCP application development support throughout the lifecycle

The TBwcet component of tool automates the measurement of execution times, running the specified tests repeatedly and providing a graphical representation of the variation in execution times. It provides a facility for processor cores to be loaded to varying degrees, which in turn loads shared resources too.

The result is an ideal platform to perform interference research, and to ultimately demonstrate that the resulting interference mitigation ensures that WCET verification requirements are met.

Other features of LDRA tool suite components providing MCP support include application analysis with TBexec, static analysis with TBvision, Data coupling and control coupling analysis, project management support for interference research with TBmanager, and LDRA’s uniquely efficient instrumentation for structural coverage analysis. Read more of how LDRA supports MCP hard real-time critical application development here.