TBexec

Real-time, closed-loop control systems across the sectors rely on the deterministic completion of defined tasks within tight time windows to gather data, process it, and update the system. That places the onus on developers to ensure that the completion of these tasks is achievable even in the worst case – a requirement that is specified in a host of safety-focused standards including DO-178C, IEC 61508, ISO 26262, and many more.

TBexec leverages proven dynamic analysis test technology to automate application-wide timing and coverage measurements and provide an intuitive graphical representation of the resulting data. For example, the “Schedule Graph” below shows the execution timing of each function.

In multicore processors (MCPs), shared resource interference makes theoretical timing calculations infeasible, requiring direct measurement on the target to ensure adequate resourcing and mitigation.

Even for single-core processors, resource contention means that first principle calculations must either be applied conservatively or refined using direct measurement principles.

TBexec automates application-wide timing and coverage measurement to provide an intuitive graphical representation of the application’s behaviour. The tool is underpinned by proven dynamic analysis technology.

Each selected application run configuration can be stored as a “profile” for subsequent reuse. Options provide for the profile to be executed leveraging instrumentation for either coverage or for timing, or with no instrumentation applied. Comparing a “timing” execution profile with one without instrumentation provides the means to demonstrate that LDRA’s efficient timing instrumentation has negligible effect on performance.

The “Coverage” profile is available to enable the analysis of code coverage for the application under test. Such an approach provides insight into which parts of the application are exercised during its execution.

Data collated during TBexec analysis is reported in several different ways:

• Schedule graph
• Timing overlap graph

• Call Times
• Call Stack
• Call Overlap (aka timing coupling)

TBexec and TBwcet together provide a complete timing assurance solution, including the objectives defined by A(M)C 20-193 for multicore processors.

TBexec captures and graphically presents function and application timing, revealing dependencies, overlaps, and concurrency effects under real conditions. TBwcet complements this by measuring Worst-Case Execution Time (WCET) of application subsets under defined scenarios, including interference conditions. This enables the impact of shared resource contention on application components to be quantified.

Used in combination, they deliver both broad behavioural insight and detailed worst-case evidence – supporting verification and mitigation objectives for multicore interference compliance.

The need for timing analysis is specified for civil aviation applications in DO-178C, and the process for multicore processors is further detailed in A(M)C 20-193 . Both documents also require data and control coupling analysis to highlight possible interference scenarios, as supported by the LDRA tool suite and proven in many successful compliant projects.

Real-time, closed-loop control systems across the sectors rely on the deterministic completion of defined tasks within tight time windows to gather data, process it, and update the system. That places the onus on developers to ensure that the completion of these tasks is achievable even in the worst case – a requirement that is specified in IEC 61508, ISO 26262, EN 50716, IEC 62304 and a host of other safety-focused standards.

TBexec is part of the LDRA tool suite and a component in a broad based provision for the development of multicore application development.

TBwcet automates the measurement of execution times, running the specified tests repeatedly and providing a graphical representation of the variation in execution times. It provides a facility for processor cores to be loaded to varying degrees, which in turn loads shared resources too.

In combination with TBwcet, TBexec provides an ideal platform to perform interference research, and to ultimately demonstrate that the resulting interference mitigation ensures that WCET verification requirements are met.

Other features of LDRA tool suite components providing MCP support include static analysis with TBvision, Data coupling and control coupling analysis, project management support for interference research with TBmanager, and LDRA’s uniquely efficient instrumentation for structural coverage analysis. Read more of how LDRA supports MCP hard real-time critical application development here.

Technical note:

Website:  Multicore (MCP) development lifecycle support: Worst-Case Execution Timing (WCET) and other considerations

Website: Multicore processors (MCP) and CAST-32A / A(M)C 20-193: Support for the development lifecycle

Technical note: Worst Case Execution Timing by measurement

Data sheet:  Worst Case Execution Timing by measurement

Video: Execution time analysis: Worst Case Execution Time (WCET) and the LDRA tool suite

Website: TBwcet

Website: ISO 26262, functional safety, and ASILs – what it all means, and how automated tools can help to achieve compliance