Andes, a Founding Premier member of RISC-V International, is a publicly-listed company and a leading supplier of high-performance/low-power 32/64-bit embedded processor IP solutions, and the driving force in taking RISC-V mainstream. Andes’ fifth-generation AndeStar™ architecture adopted the RISC-V as the base. Its V5 RISC-V CPU families range from tiny 32-bit cores to advanced 64-bit cores with DSP, FPU, Vector, Linux, superscalar, and/or multicore capabilities. The annual volume of Andes-Embedded SoCs has exceeded 3 billion in 2021 and continues to rise. By the end of 2021, the cumulative volume of Andes-Embedded™ SoCs has surpassed 10 billion.

Andes Technology is a prominent provider of high-efficiency, low-power 32/64-bit RISC-V processor cores. The 3-stage pipeline 23-Series, 5-stage pipeline 25-Series, 27-Series, and 8-stage in-order superscalar 45-Series families are based on Andes’ latest AndeStar™ V5 architecture. All of them are equipped with optional single and double-precision floating-point instruction sets. The A-prefix is Linux capable, and N-prefix supports RTOS, while D-prefix supports RISC-V packed SIMD/DSP instructions, which is developed by Andes and contributed to the RISC-V foundation. NX27V/AX45MPV are vector processors with RISC-V V-extension that are welcome by AI/Deep Learning, video, and image processing applications.

A(X)25MP, A(X)27L2 and A(X)45MP deploy L2 cache controller that improves memory transaction efficiency significantly. Furthermore, A(X)45MP, supports up to 4 cores with cache coherence, provides more computing power for heavy-duty applications. 27 and 45-Series both use “MemBoost” technology to vastly expand the bandwidth of its memory subsystem. Andes extends RISC-V with features including its own instructions to improve performance and functionality, Andes Custom Extension™ (ACE) to create instructions for customized acceleration, half-precision floating point load/store instructions to accelerate high precision arithmetic processing and enhances RISC-V PLIC (Platform-Level Interrupt Controller) with vectored interrupt dispatch and priority-based preemption to speed up interrupt handling. Andes also provides instruction trace solution that accelerates a deep analysis of code execution.

Andes Technology introduced the first ISO 26262 fully compliant RISC-V processor IP – N25F-SE in 2022 with ASIL B certification. Andes is also gearing up to unveil the ASIL-B certified D25F-SE equipped with RISC-V P-extension (SIMD/DSP) ISA draft for efficient manipulation of multiple data in a single instruction in the fourth quarter of 2023. Furthermore, Andes is working to deliver high-performance superscalar D45-SE and power-efficient D23-SE that target on mission-critical ASIL-D applications. D45-SE and D23-SE will be available in mid of 2024.

The AX65 is the first of the high-performance out-of-order AX60 series. Equipped with the 13-stage pipeline, 4 wide decode, out-of-order execution, and multi-core support, with performance higher than Cortex A75. AX65 targets the Linux application processor socket of computing, networking, and high-end controllers. AX65 will be released in Nov 2023.

All cores are available in platform packages of CPU subsystem pre-integrated with bus controller and peripheral components to facilitate SoC designs, and features such as PowerBrake, QuickNap™, WFI for additional power saving; StackSafe™ for stack overflow/underflow protection; and CoDense™ for additional code density enhancement on top of RISC-V C-extension.

With innovative micro-architecture and low-power memory structure, the AndesCore™ CPU families provide high performance and power efficiency superior to competing 32-bit/64-bit cores on the market. In addition, AndesCore™ CPU families employ various commonly used low-power design techniques to save energy and further allow SoC-level power management to regulate operating voltage and frequency for better energy/performance outcomes.