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How Safety-Critical System Developers Are Adopting RISC-V


RISC-V architecture provides unique capabilities that support the development and compliance of safety critical applications. Embedded software development teams working on functionally safe systems can leverage these features to meet standards such as DO-178C and ISO 26262 while reducing their certification burden. While aligning RISC-V’s key attributes—modularity, simplicity, and extensibility—with industry standards presents challenges, this article outlines different approaches embedded developers can use to streamline certification for safety-critical systems.

TAKE ADVANTAGE OF ISA

Unlike proprietary processor architectures, such as Arm, RISC-V uses an open instruction set architecture (ISA) developed by the University of California, Berkeley. This architecture follows reduced instruction set computing (RISC) principles, emphasizing performance and modularity in processor design and thus offering distinct advantages in the certification process. The open-standard approach eliminates the compatibility requirements that typically increase certification complexity and vendor lock-in. ISA is structured as a small base integer set, enabling developers to incorporate only the essential features

and minimize unnecessary system complexity. Additionally, RISC-V’s royalty-free licensing model eliminates cost barriers when customizing implementations, and its absence of proprietary IP reduces potential design liability concerns.

LDRA tool suite integration with Microchip’s PolarFire SoC

CLEAN SEPARATION BETWEEN HARDWARE AND SOFTWARE

Functional safety standards such as ISO 26262 require the documentation of hardware-software interfaces. RISC-V’s architectural approach facilitates compliance by clearly defining core ISA functionality and optional extensions. With this modular intent, development teams can document safety-related custom extensions while maintaining standard interface specifications for the base architecture, which simplifies requirement traceability and verification processes.

PRE-VERIFIED COMPONENTS

There’s a growing number of pre-certified RISC-V IP cores from established vendors, including Microchip, SiFive, and CAST, significantly reducing certification overhead. These components integrate essential safety features, such as advanced error detection and correction mechanisms, sophisticated watchdog timers, and robust memory protection units. Implementation teams can leverage existing certification documentation when using these pre certified cores, reducing compliance effort. For specialized applications, suppliers such as Frontgrade Gaisler provide radiation-hardened RISC-V hardware designed specifically for space. This mix of industry support, technical guidelines, and certification tools only accelerates RISC-V adoption in safety-critical systems, making it an attractive option for organizations developing next-generation applications.

IMPLEMENTING DISSIMILAR REDUNDANCY

RISC-V’s open architecture provides options for implementing dissimilar redundancy strategies for systems that must achieve DO-178C Design Assurance Level A certification. Engineering teams can deploy varying processor configurations within a single system or use different RISC-V vendor implementations while preserving architectural consistency. Additionally, they have the flexibility to integrate diverse architectures in mixed-criticality systems, where safety requirements and certification levels vary across components. These implementation approaches minimize the complexity of certification evidence required to demonstrate protection against common-mode failures.

WORST-CASE EXECUTION TIMING (WCET)

DO-178C mandates WCET analysis, specifically addressing this requirement in sections §6.3, §6.3.4,and §11.20. EASA AMC 20-193 and FAA AC 20-193 provide additional guidance for validating execution time boundaries. RISC-V’s cache memory management architecture provides unique benefits for meeting these timing requirements by supporting deterministic runtime execution. The ability to configure Level 2 cache memory as RAM enables precise control over system timing characteristics, facilitating the WCET analysis essential for certification.

Safety-critical system developers are adopting RISC-V.

DEVELOPMENT ECOSYSTEM MATURITY

Several development tools and verification environments support RISC-V-based certification activities throughout the development cycle. Advanced toolsets, such as LDRA’s target license packagefor RISC-V architectures, support requirement traceability, WCET measurements for AMC 20-193 compliance, multicore code coverage analysis on the development host and target, and integration with major RISC-V development platforms. Additionally, LDRA is highly integrated with RISC-V environments, supporting dynamic testing with silicon-level simulation and real hardware. Industry solutions like these enhance the qualification process by providing high-assurance workflows that streamline verification and documentation requirements.

REDUCED VENDOR LOCK-IN

RISC-V’s open architecture model reduces supply chain dependence by enabling diverse sourcing strategies. Engineering teams can implement equivalent processor configurations from multiple vendors, enhancing both supply chain resilience and safety case documentation. This architectural flexibility proves valuable in aerospace and automotive applications with extended lifecycles, especially when maintaining documentation for continued airworthiness or automotive safety integrity level compliance. The ability to transition between suppliers without architectural modifications simplifies recertification procedures when addressing component obsolescence.

CONSIDER RISC-V A VIABLE OPTION

The combination of RISC-V’s architectural advantages, maturing tool support, and availability of pre-certified components creates compelling opportunities for safety-critical system development. Through careful consideration of certification requirements during implementation, development teams can leverage RISC-V’s features to optimize the certification process while maintaining robust system safety and reliability standards.

 

For more information about LDRA, visit http://www.ldra.com


by
 Jay Thomas, technical development manager, LDRA.

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