Safety and security critical systems operate in environments where adherence to stringent requirements is important for ensuring the correct operation of the system, as well as its safety and reliability. Multicore processors (MCPs) improve system performance while reducing size, weight, and power consumption over single core processors (SCPs). Companies across industries aim to leverage these MCP advantages to develop new and innovative systems, however they are finding the development and verification of critical software is more complex than with SCPs. Consequently, the challenges of safety certification for multicore systems, particularly the challenge of overcoming hardware shared resource (HSR) interference, have been gaining a lot of attention.

While these challenges are new and complex, separating myth from reality about them is essential for overcoming them. In this webinar DDC-I and LDRA will discuss several myths surrounding the certification of MCP applications including:

• Shared resource interference is an impossible problem to overcome
• Shared resource interference is only a MCP problem
• Interference is never intended
• Timing variability is only a MCP problem