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Microchip Partners with LDRA for Functional Safety

Microchip Technology Inc., a leading provider of microcontroller solutions has partnered with LDRA, leader in automating software verification, validation, requirements traceability and standards compliance as a commitment to functional safety and standing up a safety culture at Microchip.  This strategic relationship has formed an innovative ecosystem between LDRA’s regulatory requirement’s expertise and LDRA’s tool suite integration with Microchip’s award-winning MPLAB® X Integrated Development Environment and MPLAB XC compilers and development workflow that ensure safety and compliant 16-bit microcontroller products to functional safety standards like ISO 26262.

Learn more about: Microchip’s Functional Safety Relevant Features – 16-bit PIC® MCUs and dsPIC® DSCs

MPLAB & TBmanager

An emphasis on functional safety and cybersecurity has arisen with the evolution of autonomous vehicles and the enforcement of safety requirements by automotive OEM manufacturers.  Integrity in the design and the verification and protection of the system are paramount.

However, developing microcontroller solutions with functional safety and security requirements can be overwhelming, especially considering standards such as ISO 26262 and J3061.  To meet this challenge, LDRA produces a safety and security “V” lifecycle model tailored to fit security and safety product development.  The LDRA V model phases address Threats and Risk Assessment (TARA); Hazards and Risk Assessment (HARA); Security and Safety Goal Requirements; Functional and Technical Security and Safety concepts, as well as Safety and Security Implementation, along the left side of the V model.  Along the right side of the V model, phases for the Verification, Validation, Assessment and then Management of Safety and Security complete the lifecycle.

Biproducts of following the V model process include artifacts like the specific set of safety and security goals, safety and security requirements, failure modes, test cases and  mechanisms for determining the level of faults that are supported and their transitions back to safe states.

Safety Security V Model

LDRA’s tool suite complements MPLAB® X, in achieving compliance standards and assurance towards functional safety and security goals, while also enabling requirements traceability.  LDRA provides traceability from multiple types of requirements, and their levels of abstractions, all the way down to the code function and test case.  This ensures that there aren’t any missing links, and unfulfilled or unverified requirements.


LDRA’s expertise identifies what the real and measurable achievements need to be, and what artifacts are required by semiconductor companies or any other supplier.  LDRA also assists the Failure Mode Effects and Diagnostic Analysis (FMEDA) coverage to show with demonstrable evidence that the functional safety requirements have been met.

The overall functional safety methodology for Microchip has been developed by LDRA for the legacy dsPIC33EP128GS7xx/8xx family of MCUs.  With scalability and reusability in mind, this methodology can also be applied to other legacy families of MCUs, as well as future Microchip MCU designs.  LDRA further assisted Microchip with the preparation of a Safety Manual that documents the functional safety characteristics of the Microchip controller in ASIL B applications and ISO 26262 compliance.

The verification of the dsPIC33EP128GS7xx/8xx functional safety diagnostics is taking place on the actual target hardware.  Diagnostic software and MCU peripherals are exercised by simulating failure conditions through fault injections.  Fault detections are then measured for effectiveness.  Additionally, LDRA provides automatic report generation and charts to track progress; LDRA also enforces conformity to automotive coding standards like MISRA, which Microchip has adopted.  Rounding out a complete functional safety solution, LDRA fully integrates with the MPLAB and dsPIC tool chain, supporting a wide range of compilers and processors.